1. Field of the Invention
The present invention relates generally to data flow in an integrated circuit, and in particular to methods and mechanisms for handling address conflicts between memory requests in a system cache located in a memory controller.
2. Description of the Related Art
Modern day mobile electronic devices often include multiple components or agents sharing access to one or more memory devices. A memory controller may be coupled to the memory device(s), and the multiple components and/or agents may access the memory device(s) via the memory controller. The memory controller may include a system cache for storing data to reduce the number of memory requests that have to access off-chip memory.
The various agents within an electronic device may make large numbers of requests to memory, and from time to time, two or more outstanding requests will target the same address, resulting in an address conflict between the requests. In some cases, a best effort agent, such as a scaler, may produce data for a real time agent such as a display. For example, a given best effort read request may be allocated in the system cache but may progress slowly in the memory system due to its low priority. If a real-time read request is received at the system cache, and the real-time read request has an address conflict with the given best effort read request, the slow progress of the best effort read request can cause an underflow issue.